Contents I. Introduction
Due to process variation, IC performance consists of two parts: nominal performance and its variation; both are important to the quality of very-large-scale-integration (VLSI) circuits. As manufacturing geometries continue to shrink, parametric yield is becoming increasingly important, especially for systems-on-a-chip, such as mixed logic and memory. Therefore, yield optimization of VLSI is a crucial ingredient for manufacturability-driven designs in a time-to-market development environment. Furthermore, improving yield hardly increases extra cost because it only involves redesign by choosing a set of optimum nominal values. Therefore, yield optimization is a preferred method as it directly translates into profits.
