An Offset Cancellation Technique for Two-Stage CMOS Operational Amplifiers

An offset cancellation technique for two-stage CMOS operational amplifiers is proposed. The auxiliary amplifiers are employed to cancel the offset voltage. The error voltage is stored on a capacitor during the cancellation phase and is canceled during the normal operation. An experimental prototype amplifier implemented in a 0.35-mum CMOS technology demonstrates that the offset voltage is reduced to 1.898 mV under a clock frequency of 200 KHz.