1. INTRODUCTION
Future Systems-on-Chip (SoCs) containing billions of transistors will allow the development of new applications, which will work in a distributed way and require reusable communication architectures offering scalable bandwidth and parallelism. Network-on-Chip (NoC) emerges as a potential tile-based architecture to meet such requirements. NoCs are communication infrastructures composed by a set of routers interconnected by communication channels, which can provide asynchronous communication between synchronous domains. An important issue for NoC-based system designers is to devise a solution of the core placement problem in order to satisfy the communication requirements.