Highly Reliable Power Aware Memory Design

In this paper, an efficient technique for designing RAMs for on chip correction of double errors integrated on H-tree memory architecture is discussed. The reliability of the proposed design is improved by 8X while the Mean Time To Failure is improved 3X while comparing to traditional Hamming codes for a 256 Mbits memory chip. The area is sacrificed for these reliability improvements, significant power savings and the performance boost.