Trenched MOSFET Vgs Uniformity Improvement through Furnace Loading Procedure

In this paper, we presented a new furnace loading procedure with specially-prepared monitor wafer (SPMW) to prevent scrapping wafers placed at top slot of the furnace boat and other slots if lot has < 25 wafers. These wafers showed V
_gs
OOS on high side. Our investigation showed that nonuniform V
_gs
behavior is due to inconsistent phosphorus atoms diffused across furnace boat. The phosphorus outgassing occurs during p-body anneal from the n-doped poly film of the wafer backside to the wafer beneath. Conventional furnace boat layout consists of oxide wafers at top and bottom slots of the boat designated as side dummy wafers (SD). If <25 wafers per lot, extra dummy wafers (ED) will be inserted at slots originally assigned to production wafers. New layout packs all wafers continuously without ED in between with additional SPMW just below SD. The wafer scrap yield was improved by at least 1% for trenched DMOS (double diffused power MOSFET).