Ka-Band Low-Loss and High-Isolation 0.13 μm CMOS SPST/SPDT Switches Using High Substrate Resistance

This paper presents 35 GHz single-pole-single-throw (SPST) and single-pole-double-throw (SPDT) CMOS switches using a 0.13
μ
m BiCMOS process (IBM 8HP). The CMOS transistors are designed to have a high substrate resistance to minimize the insertion loss and improve power handling capability. The SPST/SPDT switches have a insertion loss of 1.8 dB/2.2 dB, respectively, and an input 1-dB compression point (P1dB) greater than 22 dBm. The isolation is greater than 30 dB at 35–40 GHz and is achieved using two parallel resonant networks. To our knowledge, this is the first demonstration of low-loss, high-isolation CMOS switches at Ka-band frequencies.