A Self-Biased Operational Transconductance Amplifier in 0.18 micron 3D SOI-CMOS

We report on the design fabrication and testing of a wide range transconductance amplifier fabricated in the 0.18
μ
m MIT Lincoln Labs 3D SOI-CMOS process. The amplifier is designed to operate in subthreshold and employs self-biased cascode transistors to minimize the bias lines transversing the 3 tiers in the technology.