Statistical Pattern Recognition and Built-in Reliability Test for Feature Extraction and Health Monitoring of Electronics under Shock Loads

The built-in stress test (BIST) is extensively used for diagnostics or identification of failure. The current version of BIST approach is focused on reactive failure detection and provides limited insight into reliability and residual life. A new approach has been developed to monitor product-level damage during shock and vibration. The approach focuses is on the pre-failure space and methodologies for quantification of failure in electronic equipment subjected to shock and vibration loads using the dynamic response of the electronic equipment. Presented methodologies are applicable at the system-level for identification of impending failures to trigger repair or replacement significantly prior to failure. Leading indicators of shock-damage have been developed to correlate with the damage initiation and progression in shock and drop of electronic assemblies. Three methodologies have been investigated for feature extraction and health monitoring including development of a new solder-interconnect built-in reliability test, FFT based statistical-pattern recognition, and time-frequency moments based statistical pattern recognition. The solder-joint built-in-reliability-test has been developed for detecting high-resistance and intermittent faults in operational, fully programmed field programmable gate arrays. Frequency band energy is computed using FFT and utilized as the classification feature to check for damage and failure in the assembly. In addition, the Time Frequency Analysis has been used to study of the energy densities of the signal in both time and frequency domain, and provide information about the time-evolution of frequency content of transient-strain signal. Closed-form models have been developed for the eigen-frequencies and mode-shapes of electronic assemblies with various boundary conditions and component placement configurations. Model predictions have been validated with experimental data from modal analysis. Pristine configurations have been perturbed to quantify the degradation in confidence values with progression of damage. Sensitivity of leading indicators of shock-damage to subtle changes in boundary conditions, effective flexural rigidity, and transient strain response have been quantified. Explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, package falloff and solder ball failure. This allows the physical quantification of solder ball crack damage in the form of confidence values and provides a damage index that can be utilized for the health monitoring of solder interconnects in an electronic assembly.

Introduction

Diagnosing impending loss of functionality provides a window for the identification of potential failures and trigger repair or replacement significantly prior to failure. In this paper the system-level prognostication methodologies for electronic devices has been investigated using methodologies employing a solder-interconnect built-in reliability test, and FFT based statistical-pattern recognition, and time-frequency moments based statistical pattern recognition techniques for feature extraction and health monitoring. The Built in self test (BIST) approach is currently being applied to the testing of Digital chips and various other digital devices [Steininger 2000, Harris 2002, Hashernpour 2004, Suthar 2006], but the current version of BIST approach is focused on reactive failure detection and provides limited insight in to solder joint reliability and residual life. A new solder-interconnect built-in reliability test for FPGAs has been developed and it has been shown that the detection of the high-resistance faults that result from damaged solder joints, can be accomplished by utilizing a maximum of one small capacitor externally connected to each selected test pin or each group of two test pins.