Self-Assembly Process for Chip-to-Wafer Three-Dimensional Integration

We have proposed chip-to-wafer stacking for three-dimensional (3D) integration. To realize the chip-to-wafer 3D integration, five key technologies of through-Si interconnection and microbump formation, chip-to-wafer alignment, underfilling, and chip thinning were investigated. Three-layer stacked chips with a layer thickness of several tens microns were fabricated by using the key technologies. Each chip was serially and mechanically aligned and bonded onto a support LSI wafer. In addition, we newly introduce a stacking technique using self-assembly as a key process for advanced chip-to-wafer 3D integration. High-precision alignment with an accuracy of within 1 μm was obtained and stacking throughput can be dramatically improved by the self-assembly.