A Zero-Crossing-Based 8b 200MS/s Pipelined ADC

A zero-crossing-based 8b 200MS/S pipelined ADC is implemented in a 0.18 μm CMOS process. It uses dynamic zero-crossing detectors and digital FFs that replace the functions of opamps and comparators. The ADC draws no static current. The power consumption is 8.5mW. The FOM is 0.51pJ/step

Comparator-based switched-capacitor (CBSC) circuits were introduced in [1] as an alternative to opamp-based designs to overcome the limitations of opamps due to device and voltage scaling. Reduced device gain and signal swing make it increasingly difficult to design high-gain high-speed feedback loops with opamps. CBSC circuits replace the opamp with a comparator and a current source (see U₁ and I₁ in Fig. 25.5.1) to eliminate these difficulties and operate more power efficiently. Just as the opamp in an opamp-based design, the comparator contributes most significantly to the overall FOM in a CBSC design. Generally, a comparator must resolve the difference between 2 arbitrary voltages. The input of the comparator in a CBSC circuit, however, is not arbitrary but is a voltage ramp with a constant slope. Therefore, the comparator actually performs a zero-crossing detection. This work replaces the general-purpose comparator of CBSC circuits with a more power-efficient zero-crossing detector and demonstrates this architecture, zero-crossing-based circuits (ZCBC), with an 8b 200MS/s 1.5 b/stage [2] pipelined ADC. Figure 25.5.1: Two stages of a 1.5b/stage CBSC pipelined ADC. U₁ and I₁ perform the equivalent functionality of an opamp.