A 1.6pJ/bit 96% Stable Chip-ID Generating Circuit using Process Variations

A 128b 6.3pJ/b, 96%-stable chip-ID generation circuit using process variation is designed in a 0.13mum CMOS technology. The circuit consumes 162nW from a 1V supply at low readout frequencies and 6.34muW at 1 Mb/s. Two layout techniques are designed and fabricated to provide a performance comparison of power consumption and ID reliability