I. Introduction
Although considerable progress has been made in behavioral and high-level synthesis over the past two decades, new solutions are needed for advanced algorithm-oriented designs, such as multi-media and signal processing applications. Traditional high-level synthesis tools are effective at capturing the HDL specification by extracting a data flow graph (DFG) and mapping it directly into an architecture using structural optimization techniques, such as scheduling, resource allocation and binding [1]. However, these tools are less effective at the higher levels of abstraction. Most of these systems rely on a fixed data flow graph (DFG), extracted from the initial HDL specification, and provide limited means for modifying the initial data flow structure. In an attempt to explore other solutions the user often needs to rewrite the original specification, from which another DFG is derived and synthesized. This approach seriously limits the scope of the ensuing architectural synthesis and the quality of final hardware implementation.