Prediction of the Influence of Induced Stresses in Silicon on CMOS Performance in a Cu-Through-Via Interconnect Technology

One approach to 3D chip stacking and integration is to process filled Cu-vias into the Si and to attach them to a next level die by means of thermocompression bonding. This results in induced stresses in the silicon due to the large CTE disparity between copper and silicon, and also from the force applied during thermocompression bonding. These stresses can have an impact on the performance of the transistors and may as well result in die fracture. This paper studies these stresses through Finite Element modeling. We found that the keep-away- zone of the transistors from the copper via where transistor performance is impacted by the through-Si interconnect proximity, is proportional to the via diameter. The bonding temperature is found to be the main cause for the induced stresses during the thermocompression bonding process. The induced stresses in silicon decrease with decreasing the silicon thickness.