Two Time-Interleaved ADC Channel Structure: Analysis and Modeling

In this paper, our objective is to transmit a know-how and methods that can help the designer to develop their own models in a reasonable time. With this intention, we take the Time Interleaved ADC (TIADC) structures like example. The TIADC is a possible way to increase the ADC speed without using exotic and expensive technologies and without loosing too much in resolution. However, this structure suffers from channel mismatch effects. In this paper, we will not propose others mismatch compensation algorithms, as the aim of this work is to provide a Top-Down modeling methodology using VHDL-AMS.