Smart CMOS Charge Transfer Readout Circuit for Time Delay and Integration Arrays

This paper presents a novel CMOS charge transfer readout circuit for X-ray time delay and integration (TDI) arrays with a depth of 64. The proposed circuit uses a charge transfer readout similar to CCD; thus, the summing of the signal charges can be implemented easily compared with other typical CMOS readout circuits for TDI arrays. The weakness of TDI arrays related to defective pixels can be solved by integrating a dead pixel elimination circuit. In addition, the proposed method can be applied to a TDI arrays with large depths, so a high signal to noise ratio (SNR) can be acquired. The readout chip has been fabricated using a 0.6 mum standard CMOS process for 150times64 CdTe X-ray detector arrays. It was found that the readout circuit can effectively increase the charge storage capacity up to 1.6times10
⁹
electrons, and then provide an SNR improved by a factor of approximately 8