I. Introduction
In deep sub-micron CMOS technologies, leakage currents contribute significantly to the overall power consumption of digital CMOS circuits. In high performance applications [1] this limits the maximum number of operations per time and so the computing power. Mobile applications mainly suffer from reduced standby time if the leakage losses become significant. The sleep transistor scheme [2], [3] reduces the leakage of unused circuit blocks. In idle state, a PMOS (header) or NMOS (footer) transistor separates the circuit either from or from . Leakage reduction ratios of up to three orders of magnitude have been reported [4]. Other leakage reduction techniques like transistor stack forcing or the multiple threshold technique address only subthreshold leakage currents. The sleep transistor scheme affects all kinds of leakage currents and therefore shows the best scaling properties and the best leakage suppression among all leakage reduction techniques. However, the scheme is only beneficial if there exist submodules which can be suspended for a considerable amount of time. The reduction of the minimum power down time for which net power saving is obtained [4] and the reduction of the latency due to block activation are therefore important design issues.