A low noise Si-CMOS amplifier-multiplexer readout circuit array for imaging applications

The noises of readout circuit are analyzed and methods for decreasing noises are presented in this paper. An improved readout circuit with capacitive transimpedance amplifier (CTIA) is presented, and the correlated double sampling technology is used. The structure and operational mechanism of the circuit are detailed. Using CSMC 0.6mum DPDM CMOS, the circuit is implemented. The measured results show that the output noise is only 283nV rms at the power supply voltage 5V and the bandwidth of 1MHz. The active size of readout circuits array is 8.9 times 1.4mm
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