Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process

A multi-phase 1 GHz charge pump in 32 nm logic process demonstrates a compact area (159 × 42 ¿m²) for boosting supply voltage from twice the threshold voltage (2 Vth) to 3-4 Vth. Self contained clocking with metal-finger flying capacitors enable embedding voltage boost functionality in close proximity to digital logic for supplying low current Vmin requirement of state elements in logic blocks. Multi-phase operation with phase separation of the order of buffer delays avoids the need for a large storage reservoir capacitor. Special configuration of the pump stages to work in parallel enables a fast (5 ns) output transition from disable to enable state. The multi-phase pump operated as a 1 V to 2 V doubler with >5 mA output capability addresses the need for a gated power delivery solution for logic blocks having state-preservation Vmin requirements.

I. Introduction

With the continued scaling of VLSI technology, state storage elements in logic chips based upon cross-coupled inverting gates—flip-flops, register files, and SRAMs—have run into the limitations of requiring a minimum retention supply voltage (Vmin). At the same time, in the quest for reducing power in logic blocks (both leakage as well as dynamic power) aggressive power gating is employed. Embedded state elements in these power gated logic blocks require a separate supply voltage at Vmin to maintain state when the main supply is throttled down ( in Fig. 1). Voltage doubling charge pumps [1], [3]–[5] allow this Vmin requirement for state elements to be supported in spite of the supply voltage (Vcc) being throttled down to a value less than Vmin. Additionally, they enable the use of a single supply grid to power logic blocks with Vmin requirements satisfied by pumping up a local grid connected only to state elements. Charge pumps utilized in this fashion avoid the need for an additional external rail and the associated cost of providing an external voltage regulator. In addition distributing multiple compact charge pumps allows the support of multiple distinct Vmin requirements of logic blocks. By having the logic blocks gate the charge pump (by disabling the pump clocks) short duration requirements of Vmin greater than Vcc within the blocks (low-duty-cycle high-Vcc requirement), e.g., boost requirements in memories, can be easily supplied. Fig. 1.

Distributed charge pump supporting Vmin requirement for digital logic.