A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC

A 16-bit 125 MS/s pipeline analog-to-digital converter (ADC) implemented in a 0.18 ¿m CMOS process is presented in this paper. A SHA-less 4-bit front-end is used to achieve low power and minimize the size of the input sampling capacitance in order to ease drivability. The ADC includes foreground factory digital calibration to correct for capacitor mismatches and dithering that can be optionally enabled to improve small-signal linearity. This ADC achieves an SNR of 78.7 dB, an SNDR of 78.6 dB and an SFDR of 96 dB with a 30 MHz input signal, while maintaining an SNR > 76 dB and an SFDR > 85 dB up to 150 MHz input signals. Further, with dithering enabled the worst spur is <-98 dB for inputs below -4 dBFS at 100 MHz IF. The ADC consumes 385 mW from a 1.8 V supply.

I. Introduction

Adcs are key components in communication systems. With improvements in technology, today's mobile wireless communication systems require high-performance low-cost ADCs with emphasis on low power. Further, many of the modern IF-sampling superheterodyne communication systems require the ADC to sample input signals up to 300 MHz in order to reduce receiver complexity and lower overall system cost. Pipeline ADCs are the architecture of choice for ADCs used in such wireless communication systems, and are ideally suited for realizing 12–16 bits of resolution, 70–80dB of SNR, 85–95 dB of SFDR at 100–300 MS/s, while dissipating less than 1 W of power [1]. Also, CMOS is the preferred technology due to its lower cost and suitability for implementing switched capacitor circuits. CMOS switched capacitor pipeline ADCs are the most widely used ADCs in today's mobile wireless communication systems.