Contents I. Introduction
The cellular infrastructure market requires high clock rate, high dynamic range analog-to-digital converters (ADCs) to enable efficient, advanced architecture receive channels. For cellular base stations and other communication systems, high-performance ADCs are key for receive channel throughput efficiency. High-speed, very high dynamic range ADCs can simplify system design, reduce overall cost, and maximize receiver sensitivity. Design of these ADCs presents difficult architectural tradeoffs. A great deal of research has been done in the industry and at the university level to understand these tradeoffs and find alternative design techniques. Although high-performance ADCs have been documented with other architectures (a sub-ranging ADC in a complementary bipolar process [1]), switched-capacitor pipelines have been a consistent choice for high clock rate, high dynamic range integrated ADCs. Some of the key tradeoffs and challenges in the design of high-speed, high-linearity switched-capacitor pipeline ADCs include: 1) amplifier limitations—the tradeoff among open-loop gain, headroom, and speed; 2) MOS switch charge injection; and 3) capacitor mismatch. These are summarized below and will be discussed more completely later in the paper.
