I. Introduction
Recently, partially depleted SOI (PD-SOI) CMOS devices have emerged as one of the promising solutions for high-performance CMOS applications. It is offering many advantages over conventional bulk CMOS, such as larger due to the floating body effect (FBE), smaller junction capacitance (Cj) and less body effect [2]. However, there are many disadvantages to be overcome concerning PD-SOI CMOS devices, such as the history effect, wafer quality and cost, gate oxide integrity, self-heating, and additional option of body contact to fix the body potential. If desirable SOI CMOS device characteristics were realized using conventional bulk CMOS technology, a better solution would be available for high-performance and low-power CMOS, and especially so for system-on-a-chip (SoC) applications.