I. Introduction
The primary motivation for this work was to demonstrate feasibility of an integrated and packaged 10+ Gb/s serial link in 90-nm CMOS technology using NRZ signaling. The intended application for such links is high-density serial I/O for advanced ASICs and microprocessors operating over short and medium distances (on-board and board-to-board). High channel losses and reflections common for electrical serial links operating at 10+ Gb/s require channel equalization, which is most commonly done using transmitter feed-forward equalizer (FFE), receiver decision-feedback equalizer (DFE), and/or receiver peaking pre-amplifier [1]– [3]. The chip presented in this work equalizes the channel using a feed-forward equalizer or FFE in the transmitter and a programmable peaking amplifier in the receiver.