A CMOS V-I converter with 75-dB SFDR and 360-/spl mu/W power consumption

This work describes a method for analysis of voltage-to-current converters (V-I converters or transconductors) and a novel V- I converter circuit with significantly improved linearity. The new circuit utilizes a combination of cross-coupling and local resistive feedback for a significant, simultaneous suppression of the third- and fifth-order harmonic distortion components in the transconductor characteristics. An evaluation of the optimal circuit dimensioning is shown. Simple and robust design rules are derived for the chosen operation conditions. The transistor implementation is presented and a prototype V- I converter is realized in a digital 0.18-/spl mu/m CMOS technology. The measured spurious-free dynamic range is 75 dB in a frequency band of 10 MHz. The circuit occupies less than 0.02 mm/sup 2/ and dissipates 360 /spl mu/W.

I. Introduction

CIRCUITS that convert the voltage applied to their input terminals into output current are generally referred to as transconductors or V–I converters. These circuits are basic building blocks in many applications. The precision of the V–I conversion, with respect to the introduced distortion and noise, can be a limiting factor for the precision of the overall signal processing. There are numerous works that treat the improvement of the V–I conversion, in different application contexts and via different techniques [1]–[6]. In some recent, high performance designs [7], [8] a combination of linearization techniques is used. In this paper, first, an approach for a generalized mathematical treatment of the V–I function is suggested. It explains and confirms the potential of the combined linearization techniques to achieve better linearity. Second, a new circuit solution based on MOS differential pairs is described as an example of the implementation of that approach. Then the realization of this circuit is shown and the performance-limiting factors are discussed.