Wrapper-based bus implementation techniques for performance improvement and cost reduction

A low-cost wrapper-based bus implementation is described that performs well in system-on-chip (SOC) designs. Novel wrapper implementation techniques are used to create wrappers without embedded data buffers. The bus uses 1) a novel slave wrapper interface that supports flow control signals, 2) a write buffer switching technique for the master wrappers to achieve good performance at a small hardware cost, 3) a novel retry management technique called slave designated retry control (SDRC) to enable slow IP core connections and a livelock avoidance scheme using the SDRC technique, and 4) a novel bit-width conversion technique using data-width converters embedded in the bus multiplexers. A CPU-based SOC designed with the proposed bus showed that these techniques can increase throughput by about 14%, and reduce read and write latencies by about 16% and 11% compared to a conventional wrapper-based bus, when running a modeled average traffic pattern for this chip. The implemented results show that these techniques can reduce the hardware costs by 28% or 50% compared with two conventional wrapper-based conversion techniques. The chip is implemented using 0.15-/spl mu/m CMOS process technologies. The area for the on-chip bus is 3.3 mm/sup 2/ and the operation clock frequency is 200 MHz.

I. Introduction

The rapid growth of multimedia and Internet technologies is driving the demand for system-on-chips (SOCs). In such applications, SOCs must operate at higher throughput, have smaller chip area, and be developed more quickly. The scaling of CMOS process technologies has enabled SOCs to be run at higher clock frequencies and to have a larger number of embedded transistors. Developing SOCs more quickly, however, remains a key issue. A reliable scheme to reuse IP cores is thus important, and on-chip communication is considered a key technology for this. Many methods using on-chip buses [1]–[4] have been developed for the present, and on-chip networks [5]–[7] have been proposed for the future.