AC powered Josephson latch circuits

The design and experimental verification of a novel Josephson latch circuit are reported. This latch is powered by the same AC power as that used for the latching logic circuits, thus eliminating the additional power supply demanded by other Josephson latch circuits. A SET/RESET latch and a 2-port DATA latch with LSSD capability are reported. WRITE delays of 110 p.s. and 65 p.s., respectively, for the DATA and the SET/RESET modes of operation have been estimated using computer simulations. The data stored in the latch is read out into the SLAVE circuit before the AC power supply waveform completes its polarity transition; thus, the read operation does not contribute any delay to the machine cycle. Experimental latch circuits have been fabricated using a 2.5 /spl mu/m Pb-alloy process. The experimental results are discussed. The experimental latch has been operated at cycle times approaching 1 ns and the risetime of the current transfer in the latch storage loop is measured using on-chip sampling to be about 100 p.s., in good agreement with computer simulations.