An Optimally Designed Process for Submicrometer MOSFET's

An n-channel MOS process has been optimized to yield desirable characteristics for submicrometer channel-length, MOSFET's. Process/device simulation is extensively used to find an optimized processing sequence compatible with typical production-line processes. The simulation results show an excellent agreement with experimental data. We have obtained long-channel subthreshold characteristics, saturation drain characteristics up to 5 V, and a minimized substrate bias sensitivity for transistors with channel lengths as small as 0.5 /spl mu/m. The short-channel effects have been also minimized. A new self-aligned silicidation technology has been developed to reduce the increased resistance of diffused layers with down-scaled junction depths.