Abstract:
The design of a 96-stage, programmable binary-analog correlator is described. An array of charge coupled device (CCD) delay lines of differing lengths perform the delay a...Show MoreMetadata
Abstract:
The design of a 96-stage, programmable binary-analog correlator is described. An array of charge coupled device (CCD) delay lines of differing lengths perform the delay and sum function. Merging of several CCD channels is employed to reduce the active area. This device architecture allows simplified output detection while maintaining good device performance at high speeds (5-10 MHz). Experimental results indicate a 50 dB broad-band dynamic range and excellent agreement with the theoretical processing gain (19.8 db) when operated at a 6 MHz sampling frequency as a sequence matched filter pseudorandom noise.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 17, Issue: 1, February 1982)