A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell

This paper reports a 1-V 128-kb four-way set-associative CMOS cache memory implemented by a 0.18-/spl mu/m CMOS technology using wordline-oriented tag-compare (WLOTC) structure with the 10-transistor tag cell usually for content-addressable memory (CAM) for low-voltage low-power VLSI system application. Owing to the WLOTC structure with the CAM 10-transistor tag cell for accommodating the one-step hit/miss generation and the dynamic pulse generators for realizing read-enable signals, a small hit access time (3.5 ns), low power consumption (4.1 mW at 50 MHz), and good expansion capability without sacrificing speed have been obtained.

I. Introduction

LOW POWER and low voltage have become an unavoidable requirement for portable computers and wireless communication systems today. Cache memory is a key memory device in CPU-related VLSI systems, communication networks, and advanced DRAMs [1], [2] for achieving high data transfer rates. In these VLSI systems, cache memory usually consumes a majority of power provided. Low-power cache memory is very important for achieving the low-power requirements. There are three types of cache memory depending on the technology adopted: fully associative mapping [3], direct mapping [4], and set-associative mapping [5]. Among these three, the fully associative mapping technique has the best hit rate, however, its access time is the longest and its power consumption is the largest. The direct mapping technique has the shortest access time, but its hit rate is the worst. The access time and the hit rate of the set-associative mapping technique are between the two extremes. The set-associative mapping technique has been frequently applied to realize cache memory. Until now, cache memory chips have usually been implemented using the bitline-oriented tag-compare (BLOTC) structure [5], [6], where for each bitline a sense amplifier is required. When the size of the cache memory is large, the speed of its sense amplifier is slow due to the large parasitic capacitance associated with the bitline. In addition, the signal from the output of the sense amplifier needs to be compared with the index to produce the hit/miss signal. This two-step procedure in the generation of the hit/miss signal can be slow when the size of the cache memory is large. In this paper, a 1-V 128-kb four-way set-associative CMOS cache memory implemented by a CMOS technology using the wordline-oriented tag-compare (WLOTC) structure with the 10-transistor tag cell usually used for content-addressable memory (CAM) for low-voltage low-power VLSI system application is reported. It will be shown that, owing to the WLOTC structure with the CAM 10-transistor tag cell and the dynamic pulse generators for realizing read enable signals, a small hit access time (3.5 ns) and low power consumption (4.1 mW at 50 MHz) have been obtained. In the following sections, the cache memory design based on the WLOTC structure with the CAM 10-transistor tag cell for accommodating the one-step hit/miss signal generation is described first, followed by performance, discussion, and conclusion. Fig. 1.

Block diagram of the 1-v 128-kb four-way set-associative cmos cache memory.