A 256/spl times/256 CMOS differential passive pixel imager with FPN reduction techniques

A 256/spl times/256 passive pixel imager has been implemented in a CMOS 0.6-/spl mu/m technology. A column-parallel differential architecture with a correlated double-sampling output circuit removes the smear-like effects of a parasitic current that plagues passive pixels, 0.1% pixel-to-pixel and 0.4% column-to-column fixed-pattern noise are achieved.