Stage-based frame-partitioned parallelization of H.264/AVC decoding

Strong demands for high resolution video services lead to active studies on high speed video processing. Especially, widespread deployment of multi-core systems accelerates researches on high resolution video processing based on parallelization of multimedia software. In this paper, we propose a novel parallel H.264/AVC decoding scheme on a homogeneous multi-core platform. Parallelization of H.264/AVC decoding is challenging not only because parallelization may incur significant synchronization overhead but also because software may have complicated dependencies. To overcome such issues, we propose a novel approach called Stage-based Frame-Partitioned Parallelization (SFPP). In SFPP, we divide a frame into multiple partitions, and execute them in a pipelined fashion. To reduce synchronization overhead, a separate thread is allocated to each stage in the pipeline. In addition, an efficient memory reuse technique is used to reduce the memory requirement. To verify the effectiveness of the proposed approach, we parallelized FFmpeg H.264/AVC decoder with the proposed technique using OpenMP, and carried out experiments on an Intel Quad-Core platform. The proposed design performs better than FFmpeg H.264/AVC decoder before parallelization by 53%. We also reduced the amount of memory usage by 65% and 81% for a high-definition (HD) and a full high-definition (FHD) video, respectively compared with that of a popular existing method.

I Introduction

Demands for high resolution video processing techniques are rapidly increasing as high-definition digital broadcasting services are widely provided. Therefore, standards and techniques for video compression and decoding are being actively developed. One of the most popular video codec standards is H.264/AVC. One main advantage of H.264/AVC is that it is capable of providing good video quality at substantially lower bit rates than previous standards. However, it is very challenging to achieve high performance by a software implementation because its complexity is pretty high. Therefore hardware implementations have been used commonly. Recently, enhancing performance through intelligent parallel processing with multiple cores integrated in a single chip is widely adopted. Since a multi-core system typically has better power efficiency than a single core system with a comparable processing power, it is expected that many high performance embedded systems will adopt multiprocessor system-on-chip platforms soon. Even though multi-core systems will provide potentially ample computation power, it is not straightforward to achieve such high performance because efficient parallel programming for a multi-core system is difficult. Thus, it is crucial to re-write an existing software implementation into a new implementation which is more suitable for parallel processing. Also, it is very important to understand the target multi-core platform to achieve high performance. Understanding a target platform includes understanding of not only the processor itself but also the memory system and the on-chip interconnection system.