A novel bridge chip between an ATM and ethernet for ADSL in home networks

This study presents a novel bridge chip between an asynchronous transfer mode (ATM) and Ethernet for an asymmetric digital subscriber line (ADSL) in home network which fabricated in a standard 0.18-mum 1P6M CMOS process. The proposed bridge chip is an ASIC designed with hardware description language (HDL) and fabricated using a cell-based digital IC design flow. The proposed chip merges two independent chips; transmitter-end and receiver-end chips, into a single chip, and eliminate the RISC processor to reduce production cost. Moreover, system stability and transmission capacity are enhanced due to the small chip area. Chip specifications are a power supply of 1.8 V and system operating frequency of 50 MHz.