High-Performance Modulators and Switches for Silicon Photonic Networks-on-Chip

The stringent on- and off-chip communications demands of future-generation chip multiprocessors require innovative and potentially disruptive technology solutions, such as chip-scale photonic transmission systems. A space-switched, wavelength-parallel photonic network-on-chip has been shown to equip users with high-bandwidth, low-latency links in an energy-efficient manner. Here, experimental measurements on fabricated silicon photonic devices verify a large set of the components needed to construct these networks. The proposed system architecture is reviewed to motivate the demanding performance requirements of the components. Then, systems-level investigations are delineated for multiwavelength electrooptic modulators and photonic switching elements arranged in 1 × 2, 2 × 2, and 4 × 4 formations. Compact (~10 ¿m), high-speed (4 Gb/s) modulators, having a large degree of channel scalability (four channels demonstrated), are demonstrated with excellent data integrity (bit error rates (BERs) <10^-12). Meanwhile, switches are shown to transfer extensive throughput bandwidths (250 Gb/s) with fast switching speeds (<1 ns) and sufficient extinction ratios (>10 dB). Data integrity is also verified for the switches (BERs < 10^-12) with power penalty measurements amid dynamic operation. These network component demonstrations verify the feasibility of the proposed system architecture, while previous works have verified its efficacy.

I. Introduction

Microprocessors have enjoyed many decades of steady performance gains and speed increases due in large part to progress in CMOS device integration and increased instruction-level parallelism. Nevertheless, as a result of diminishing returns in traditional performance-scaling techniques and practical power limitations, modern chip design is shifting focus away from continued advancements in uniprocessor performance toward processor-level parallelism. Chip multiprocessors (CMPs), which leverage parallelism to perform the program execution by integrating two or more processor cores onto the same chip, have emerged as the new paradigm [1]–[4]. Consequently, new fields of research are emerging to address the many challenges in implementation and scaling brought about by the growing number of cores in the processor—challenges that can be fundamentally different from those faced during the uniprocessor era.