Automatic synthesis of fault trees for computer-based systems

This paper introduces a graphical design language, RIDL (the Reliability Imbedded Design Language) for modeling digital systems. In RIDL, redundancy and failure information are embedded within block diagram schematics without appreciably altering the physical block-diagram models typically used by design engineers. A system schematic in RIDL has all of the information needed for reliability analysis, thus obviating the need for additional textual descriptions. A dynamic fault-tree model can be automatically synthesized from a RIDL system model. The synthesis procedure for a fault-tree of the system is described. Designers can use the synthesized fault-trees to perform reliability (and thus tradeoff) analyses at an early conceptual design stage. The potential of this approach is demonstrated by two example systems.