I. Introduction
To develop a high performance radiation-hardened logic VLSI, such as a microprocessor operating at a clock frequency of 100 MHz or higher, it is necessary to mitigate single-event-transients (SETs). Of the parameters that characterize a SET, the pulse width draws much attention because its value is often used as a critical parameter in designing SET-mitigating circuits. In [1] and [2], it is experimentally demonstrated that a width of a SET pulse induced in a logic circuit fabricated using a bulk CMOS process varies depending on an LET of irradiated particles, and also that the pulse widths are distributed under constant-LET ion irradiation.