Optimization for SEU/SET Immunity on 0.15 $\mu$m Fully Depleted CMOS/SOI Digital Logic Devices

We designed logic cells hardened for SEUs/SETs using hardness-by-design (HBD) methodology with OKI's 0.15 mum Fully Depleted CMOS/SOI commercial process and these cells were evaluated with sample devices. Our previous work demonstrated that SET-free inverters could be successfully applied as SEU-immune latches. In this work, the logic cells were optimized for SEU/SET immunity up to an LET of 64 MeV/(mg/cm
²
), demonstrating that the process was suitable for space applications with a little penalty