Gated-diode study of corner and peripheral leakage current in high-energy neutron irradiated silicon p-n junctions

It will be shown that an analysis of gated-diode (GD) structures enables to investigate the radiation damage in different parts of p-n junctions in a CMOS technology. This is important as the peripheral, especially corner, p-n junction leakage at reverse voltage sets the leakage and power consumption of state-of-the-art integrated circuits (ICs) and the DRAM retention time. One GD enables to extract the radiation-induced peripheral leakage-current defined by the isolation surrounding the active p-n junction, while two GDs with different dimensions-the corner leakage. The method is applied to junctions fabricated in different silicon substrate types and irradiated by 1-MeV equivalent neutrons with fluence (/spl Phi/) ranging from 5/spl times/10/sup 11/ to 5/spl times/10/sup 13/ n/cm/sup 2/. While for low to moderate /spl Phi/ the significance of the peripheral leakage-current decreases, a rebound occurs for the higher /spl Phi/ investigated due to the increase of the bulk peripheral leakage and of the corner component.