Radiation hardness perspectives for the design of analog detector readout circuits in the 0.18-/spl mu/m CMOS generation

This paper presents a study of the ionizing radiation tolerance of analog parameters of 0.18-/spl mu/m CMOS transistors, in view of the application to the design of front-end integrated circuits for detectors in high-energy physics experiments. Static, signal, and noise performances of devices with various gate dimensions were monitored before and after irradiation up to a 300-kGy(Si) total dose of /sup 60/Co /spl gamma/-rays. Different device biasing conditions under irradiation were used, and the relevant results are discussed. A comparison with previous CMOS generations is carried out to evaluate the impact of device scaling on the radiation sensitivity.