A 5.8-GHz High-Frequency Resolution Digitally Controlled Oscillator Using the Difference Between Inversion and Accumulation Mode Capacitance of pMOS Varactors

This paper proposes an oppositely coupled varactor pair and reports the measured results for applying to a test digitally controlled oscillator (DCO). The pair exploits the differences between the accumulation region capacitance and inversion region capacitance of pMOS varactors. The novel varactor pairs provide much smaller switchable capacitances than those of other approaches, and hence, the test DCO for verifying the property of the pair achieves the high-frequency resolution. The pairs and test DCO are implemented in a 0.18-μm CMOS process. The switchable discrete capacitance of 32 aF is obtained by using the novel varactor pairs, and the test DCO has a frequency resolution of about 110 kHz at 5.8 GHz. Furthermore, ΔC of 4-aF and 14-kHz frequency resolution can be obtained through the dithering processes. The test DCO achieves a low phase noise of -117.6 dBc/Hz at 1-MHz offset from 5.8 GHz.

I. Introduction

Recent research in many RF and analog integrated circuits has focused on a fully integrated system-on-chip (SoC). For high integration and low cost, many RF/analog blocks are substituted by digitally controlled blocks, such as digital transmitters, discrete time analog filtesr, digital phase-locked loops, and sub-sampling receivers [1]–[4]. One of the most vigorous research fields is all-digital phase-locked loop (ADPLL) circuits. Analog frequency tuning, in the conventional voltage-controlled oscillators (VCOs), is not compatible with deep-submicrometer CMOS processes because of very limited voltage headroom and difficulties of analog interface for the integration [5]. Digital frequency tuning has been proposed as the solution of high reliability and high integration. The digitally controlled oscillator (DCO), a vital block of the ADPLL, is one of the viable approaches to the implementation of the RF portions, which are compatible with digital portions. The performances of the DCO, such as the frequency resolution and phase noise, have a significant impact on those of the ADPLL. Since the phase noise of the DCO is a function of the frequency resolution limited by the value of unit switchable capacitor [6], some research has been focused on minimizing the unit switchable capacitance. It is a useful method to utilize the two different sizes of pMOS varactor for obtaining the smaller unit capacitance [7]. Although very small differences of pMOS sizes make much smaller, it may have large process dependency because of using very small differences of the size. The other approach of minimizing the unit switchable capacitor is using the different kind of MOSFET varactor [8]. In this method, an nMOS varactor makes a pair with a pMOS varactor. It utilizes the difference between operation modes of pMOS and NMOS, such as inversion and depletion mode. Using the nMOS may cause the problems of WELL isolation and flicker noise that can degrade the phase noise [5].