64 Mb bubble memory chip architecture

A 64 Mb bubble memory chip architecture using 1.4 μm × 1.6 μm cell size ion-implanted tracks and the dual gate with block replicate and swap functions is described. The memory chip is composed of sixteen 4Mb blocks, which have 1160 minor loops with the bit storage of 4097. The one major line-minor loops organization and even-odd structure are used to compose the minor loops and a major line without using bad tracks. A chip carrier with matrix diodes is connected with the memory chip by CCB bonding method to reduce the pin number of the memory module. A new pulse drive method with the matrix connection is proposed to drive 16 blocks in parallel with small number of drive circuits.