A Josephson four-bit full adder using direct coupled functional gates

A Josephson 4-bit full adder circuit using functional direct coupled gates has been designed and studied through computer simulations. The circuit consists of only 27 gates taken from a complete logic family composed of OR, AND, EXOR and MAJORITY gates. The proposed adder scheme needs 180 Josephson junctions and 150 thin film resistors. The computed critical path delay was found 180 ps/4bits for carry propagation, with a power dissipation estimated to be less than 100 μW on the basis of a Nb/Pb-In technology with 4 μm minimum linewidth and with a Josephson current density of 1000 A/cm
²
. The worst case total add time for the 4 bits has been found less than 300 ps.