Analysis and optimization of write channel front end for above 1 Gb/s recording

A system level model was developed to simulate the overall write process and study pattern dependent nonlinearities. It was found that in order to reduce field NLTS, we need a large peak current, fast rise time, long-lasting overshoot, large RPM, low interconnect impedance and large voltage supply. Design tradeoffs are explored extensively through a quadratic DOE. An improved slew rate is more efficient in achieving 1.2 Gfr/s at 15 k RPM than that of a large peak current. Both larger overshoot duration and lower interconnect impedance reduce the write driver voltage headroom requirement.