A generalized HSPICE/sup TM/ macro-model for pinned spin-dependent-tunneling devices

This work presents the first generalized circuit macro-model for a pinned Spin-Dependent-Tunneling (SDT) device. The macro-model is realized as a four terminal sub-circuit which emulates SDT device behavior over a wide range of sense and word line currents. This model accurately represents the nonlinear and hysteretic nature of an SDT device and HSPICE/sup TM/ simulations of memory circuits using this model show expected outcomes. The model is flexible and relatively simple: ranges of the write/read currents and device resistance values are incorporated as parameterized variables and no semiconductor devices are used within the model.