Nanoscale Characterization of Gate Leakage in Strained High-Mobility Devices

Epitaxial growth of strained layers used for highspeed electronic devices can induce surface roughness, which impacts gate dielectric properties. To precisely understand the effect of roughness on the quality and reliability of dielectrics, high-spatial-resolution characterization techniques are required. In this paper, we use conductive atomic force microscopy (C-AFM) to enable gate leakage analysis at the nanoscale in fully processed high-mobility strained Si MOSFETs. This is achieved by the selective removal of the gate from the dielectric, followed by nanoscale C-AFM analysis of the dielectric surface. A Hertzian contact model has been used to account for the tip-sample contact area in order to extract the current density. The techniques are applied to strained Si and bulk Si devices with different surface morphologies and macroscopic electrical data. The results suggest that materials exhibiting long-scale surface undulations are prone to degraded dielectric properties because gate leakage is increased at the highly sloped regions of the roughness. This effect is masked during conventional macroscopic electrical measurements. The increasing leakage also leads to compromised dielectric reliability. Dielectric lifetime was assessed through device stressing and has been found to be related to the level of surface roughness induced by the underlying substrate.