I. Introduction
Recently, polycrystalline-silicon thin-film transistors (poly-Si TFTs) have attracted considerable attention because of their diversity of applications, including nanowire transistor, nonvolatile memory, and 3-D circuit integration [1]–[7]. One effective approach to obtaining high-performance poly-Si TFTs and enhancing device density is to scale down the channel length. However, it is difficult to reduce channel length due to the limits of photolithography resolution. Therefore, vertical-channel thin-film transistors (VTFTs) have been widely researched and developed to overcome the limits of photolithography [8]–[10]. In these previous works, VTFTs have shown great potential for 3-D integration since the channel lengths are determined by the thicknesses of the poly-Si or silicon-dioxide film, instead of photolithographic process limitations. However, these works using asymmetric source/drain (S/D) have encountered circuit design difficulties. S/D parasitic series resistance and contact resistance remain problems for device scaling and reduce device performance.