I. Introduction
Conventionally, rapid thermal processing (RTP) is used for forming ultrashallow and low-resistivity source/drain (S/D) junctions to suppress short-channel effect and boost device performance in nanoscale complementary metal–oxide–semiconductor (CMOS) devices [1]. Unfortunately, as the device is scaled down to a 65-nm node and beyond, due to the limitation of thermal diffusion and solid solubility, the extrinsic S/D sheet resistance and the shallow junction depth after RTP cannot meet the requirements of these deep nanotechnology again [2]. Therefore, some technologies with higher activation ability such as flash-lamp annealing and/or laser spike annealing (LSA) have been studied to replace or combine the RTP for S/D diffusion-free dopant [3].