Contents I. Introduction
In recent years, the scaling of MOSFETs has been stymied by the increase in dissipated passive power with reducing the device dimensions, which stems from short-channel effects [1], [2]. Therefore, the need for novel devices, which can potentially provide a reduced dissipated power at switching speeds comparable to Si MOS devices looms increasingly large. Tunneling FETs (TFETs) have gained significant attention as promising candidates to replace MOSFETs [3]–[5]. TFETs consist of gated p-i-n structures, e.g., a p-doped drain (source), an intrinsic channel, and an n-doped source (drain). The carrier injection from the highly doped source into the channel relies on band-to-band tunneling (BTBT) at the reversed-biased source–channel junction. TFETs have been theoretically shown to exhibit a steep turn-off, below the thermal limit of 60 mV/dec, and a sufficiently high on-current comparable to that of Si MOS devices, depending on the host semiconductor [3]–[5]. To date, BTBT has been observed in carbon nanotubes [6], and TFETs using Si [7] as the host semiconductor have shown subthreshold slopes (SSs) below 60 mV/dec. However, the on-currents in these devices are several orders of magnitude smaller by comparison to conventional MOSFETs, and the devices show ambipolar characteristics owing to BTBT at both source–channel and drain–channel junctions. Various device geometries, such as nanowire (NW) TFET [8], or different materials, such as SiGe [9] and Ge [9], [10], have been advanced in an attempt to increase the device current.
