Sub-50-nm Dual-Gate Thin-Film Transistors for Monolithic 3-D Flash

The feasibility of using sub-50-nm dual-gate thin-film transistors (TFTs) for monolithic 3-D integrated flash memories is shown. Silicon-based TFTs with the smallest length and width demonstrated to date have been assembled into series strings of up to 64 cells. Read- and program-pass disturbs, the bane of any nand charge-trap flash approach, have been extinguished. The ability to independently optimize the ONO structure from pass disturbs results in excellent endurance and retention after cycling. Monolithic 3-D integration is ensured through close-to-zero source/drain diffusion at temperatures required for layer stacking. Further scalability is assured through the excellent electrostatic control that results from the cell's elemental structure. Finally, the combination of ldquoCMOS-friendlyrdquo materials and tried-and-trusted low-power program and erase mechanisms makes this approach a powerful technology contender for post- nand 3-D flash. From all nonfloating-gate monolithic 3-D approaches being touted, this is the first where a sub-50-nm device has been shown to withstand the temperature budget of subsequent layers.