The Effect of Gate Oxide Processes on the Performance of 4H-SiC MOSFETs and Gate-Controlled Diodes

The effect of different gate oxide processes on the performance of 4H-SiC MOSFETs has been studied. These processes include different gate oxide depositions (high-temperature oxide, low-temperature oxide, and plasma-enhanced chemical vapor deposition oxide) and annealing processes (oxygen, NO, and $\hbox{CO}_{2}$). Various MOS device parameters, particularly, threshold voltage, subthreshold slope, field-effect electron mobility, sheet electron carrier concentration, and Hall mobility, are correlated with various process steps.

I. Introduction

High-voltage 4h-sic power switching devices have been explored and developed over the last few years, with continuous improvement in performance. However, one of the key obstacles in SiC power MOS devices, such as the power MOSFET and the IGBT, is the inferior electrical characteristics of /4H-SiC interface, when compared with Si MOS, despite many years of process development among research groups across the world. In particular, on the (0001) surface, the trap density is high, which results in low inversion electron mobility and, thus, high channel on-resistance. This high channel resistance is particularly detrimental to the ON-state performance of SiC power MOSFETs with a breakdown voltage of 1200 V or lower.