I. Introduction
Driven by the limitation of the gate-dielectric scaling [1] and by the enormous rise in the cost of lithography equipment, there is an increasing interest in exploiting other means of advancing CMOS instead of simply reducing gate length. This includes consideration of novel MOS device structures and implementation of new materials. Strain engineering, in particular, can be instrumental in improving electron and hole mobility, thus leading to better current drive and higher cutoff frequency [2]. As one option to provide such strain enhancement, SiGe substrate engineering including bulk MOSFET on Si/SiGe [3] and Si/SiGe/Si heterostructures on insulator [4] can be adopted. This approach, although effective, raises serious concerns about defects generated within the thick gradually relaxed SiGe buffer layer, which may propagate into the silicon device layer, above, as misfit dislocations. Other means of introducing strain through material stresses is less prone to defect formation but has a limited effectiveness in device structures, which have a strong strain reference to the bulk substrate; this does not only refer to bulk MOSFETs but also to silicon-on-insulator (SOI) transistors [5], [6].