Effect of Gate Overlap and Source/Drain Doping Gradient on 10-nm CMOS Performance

This brief investigates the effect of gate overlap and source/drain (S/D) doping gradient on the switching delay of prospective 10-nm CMOS digital circuits. A two-dimensional mixed-mode simulation is used to extract switching delays, taking both the resistance (series) and capacitance (overlap) effects into account. It is shown that for abrupt S/D profiles, optimum performance is obtained at a gate overlap of about 1 nm/edge, depending on the capacitive loading. Underlap is undesirable due to current degradation from the ungated region. It is further shown that a graded S/D doping profile degrades the switching performance. For the same OFF current, a doping gradient les 3 nm/dec is required to avoid significant degradation of switching delays under optimum gate overlap conditions